Experiment 01 · semiconductor visualization

Chip Visualizer · 3nm

Peel a 3nm chip from package to GAA transistors, then trace SoC traffic and thermal behavior.

Live specimenLayered process stack

CF·5 Quantum Core

Experiment 01 · semiconductor visualization

An interactive 3D die explorer that peels a 3nm chip from package to GAA transistors, then maps its SoC traffic and thermal behavior.

Peel the stackLayered

What it reveals · from structure to behavior

A chip becomes legible when its layers and signals can be explored.

The study connects manufacturing structure with runtime behavior, so the object is understood as one working system.

Separate nine layers from the FC-BGA package through GAA nanosheet transistors, copper routing and passivation.

Move across compute, graphics, neural processing, cache, memory and I/O blocks in one decapped floorplan.

Reveal signal traffic, thermal state, layer specifications and the relationships that make the chip operate.